Simulation and analysis of various parameters of gate all around junction less nano-wire FET

Abstract

All existing transistors are based on the use of semiconductor junctions formed by introducing doping atoms into the semiconductor material. As the distance between junctions in modern devices drops below 1Onm, extraordinarily high doping concentration gradients become necessary. For this reason, a new device is proposed which has full CMOS functionality and is made by using nano-wires. They have near-ideal sub-threshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors. Among several types of field effect transistor, gate all around junction less nano wire FET (GAA JL NW FET) is the recently invented one. In this paper, we analyze the Drain current characteristics of GAA JL NW FET with respect to the channel length for different materials such as Si, GaAs, lnAs, lnP and so on. We also analyze the threshold voltage of this newly invented FET for different materials and calculate for which material this voltage is minimum by MATLAB programming. Temperature dependency of this FET is also deeply zed.